1. Field of the Invention
The present invention relates to a pulse input device, and particularly to construction of an input memory for temporarily storing information on past records of input signals and construction of a sequencer.
2. Description of the Prior Art
A pulse input device receives signals outputted from a plurality of external machines and tools, and detects change of these signals or, events and times on which these signals are changed, or event times, (hereinafter these are called "Input Information"), then outputs them to the CPU.
The pulse input device in combination with a control device detects operational states of various machines.
A conventional pulse input device of this sort, is disclosed in Japanese Patent Laid-Open Specification No. 63-295974. FIG. 1 is a schematic construction diagram of the pulse input device disclosed in the literature. In this diagram, signals outputted from external machines and tools (not shown) are inputted to an input circuit 707 as input signals 704. The input circuit 707 samples the input signals 704 at predetermined periods, then outputs them to a input memory 708. The input memory 708 temporarily stores input information sampled at predetermined times. A command memory 705 mainly stores a plurality of instruction commands (hereinafter they are called "Commands") and process results.
These commands are instructions for operating a pulse input device 701. Incidentally, rewriting of the commands in the command memory 705 is carried out by a CPU 703 through a bus 702. A timer counter 706 outputs standard time information. Moreover, a sequencer 709 scans in the command memory 705, and reads the plurality of commands successively, then executes these commands. The sequencer 709 controls the pulse input device 701 over all. As shown by a portion in a frame of a dotted line in FIG. 1, the pulse input device 701 comprises the input circuit 707, input memory 708, command memory 705, sequencer 709 and timer counter 706.
FIG. 2 is a schematic construction diagram of the sequencer 709 shown in FIG. 1. In FIG. 2, a program counter 710 designates addresses stored in the command memory 705, and a command register 712 temporarily stores a command corresponding to a content of the address designated by the program counter 710. A controller 713 decodes a command stored in the command register 712. Moreover, an arithmetic circuit 711 executes a calculation between a standard time information and an input signal information stored in the input memory 708. Namely, as shown by a portion in a frame of a dotted line in FIG. 2, the sequencer 709 is composed of the program counter 710, the command register 712, the controller 713 and the arithmetic circuit 711.
Next, in operation of the conventional pulse input device having the construction as described above, problems on construction and operation of the sequencer 709 will be described.
FIG. 3 is a flowchart of operational procedures when the sequencer 709 in the pulse input device processes commands. FIG. 4 is a timing chart illustrating when the sequencer 709 executes the commands. In FIG. 3, steps shown by rectangular frames, S1, S3, S5, S6, S7, S9, S11 and S12 require one system clock to be executed, respectively. Moreover, steps shown by diamond-shaped frames such as S2, S4, S8 and S10 are executed in combination with the steps S1, S3, S7 and S9, respectively. Accordingly, one system clock is required for each of these combination steps (S1 and S2, S3 and S4, S7 and S8, and S9 and S10) to be executed. Furthermore, in the command memory 705, six commands, CMD1 through CMD6, are stored.
The sequencer 709 scans in the command memory 705 and successively reads the commands stored therein. For the execution of the commands, the input signal information in the input memory 708 is optionally read. The arithmetic circuit 711 carries out the operation on the standard time information and input signal information read from the input memory 708. Then, the operation result obtained is outputted to the command memory 705. The operation as described above is repeated. Moreover, the sampling of the input signal 704 is carried out at every period of a sampling clock of predetermined periods. The sampling period is independent of a period in the command execution.
The time required for execution of an EGDE command as shown in FIG. 3 depends on the existence of an event at step S4. When the event is found, the execution required 4 system clocks at the steps S1 and S2, S3 and S4, and S5 and S6. and when not found, the execution requires 3 system clocks at the steps S1 and S2, S3 and S4, and S12. At the same time, a time required for execution of a WIDTH command as shown in FIG. 3 depends on the existance of an event at the step S8 and the suitability of a time when the event occurs. When the occurrence time is suitable, the execution requires 4 system clocks at the steps S1 and S2, S7 and S8, S9 and S10, and S11, and when the event is not found, the execution requires 3 system clocks at S1 and S2, S7 and S8, and S12.
Even when the same command is executed, the number of system clocks required depends on the flow of process, thus the execution of successive commands cannot be carried out at a constant period. To the contrary, the sampling of the input signals 704 is carried out at predetermined period. Accordingly, when an instruction whose execution time is short because of the process flow of command, for example, a command such as NOP is executed successively, it is difficut to keep a constant relation between the sampling period of input signals and the execution start time of command. Namely, it is possible that the reading of the input signal information is executed before the sampling is executed predetermined times. In this case, since the input signal information already sampled predetermined times is read at a time, the information read may overlap.
To solve the above mentioned problem, as shown in FIG. 4, command scan start signals inputted at predetermined periods are used to start the command scan in response to the signals. Namely, in the command scan method, commands are started not successively, but in response to the command scan start signals. In this case, it is possible to keep a constant relation on time between the sampling period of the input signals and the period of the command scan start signals. However, when command rewriting in the command memory is carried out, the command scan start time is shifted between commands before and after the rewriting process. Moreover, the shift causes misreading or overlapped reading so that it is difficult to carry out correct reading.
FIG. 5 is a diagram to show a case in which information in the input memory is overlooked in reading by the rewriting of commands. In the same drawing, four kinds of input signal information, respectively sampled at a time designated by 1, are read by the execution of a command 4 in the n-th command scanning. These four kinds of input signal information are sampled after the start of execution of the command 4 in the (n-1)th command scanning. Next, in the (n+1)th command scanning, a command 3 is rewritten into a command requiring a longer execution time than that of the command 3 in the n-th command scanning, for example, EDGE command. Accordingly, since a start time of execution of the command 4 in the (n+1)th command scanning is later than a start time thereof in the n-th command scanning, four kinds of input signal information are read at a time designated by 2 when the command 4 is executed in the (n+1)th command scanning. As the result, input signal information sampled at a time designated by 3 is overlooked in reading.
FIG. 6 is a diagram to show a case in which input signal information is read overlappedly by rewriting commands. In the same drawing, four kinds of input signal information designated by 1 are read in execution of a command 4 in the n-th command scanning. The four kinds of input signal information are sampled after execution of the command 4 in the (n-1)th command scanning.
Next, in the (n+1)th command scanning, a command 3 is rewritten into a command requring a shorter execution time than that of the command 3 in the n-th command scanning, for example, NOP command. By the rewriting, an execution start time of the command 4 based on a start time of the command scanning in the (n+1)th command scanning becomes earlier then an execution start time of the command 4 based on a start time of command scanning of the command 4 in the n-th command scanning. Accordingly, in the execution of command 4 of the (n+1)th command scanning, three kinds of input signal information designated by 2 and input signal information ( 1) sampled at the latest time in the input signal information designated by 1 are read. The input signal information designated by 1 and 1 is already read at a time of the n-th command scanning. Accordingly, the input signal information is read overlappedly from the input memory. To solve these problems, start times at which the respective commands are executed are written into the command memory, and input signal information which is sampled after execution of the previous command is selected by using the information on the start times written so as to read only the input signal information selected. However, in this method, it is necessary to write values of a timer counter into the command memory at every end of the command execution, so the process becomes complicated. Moreover, in reference to the input memory, it is necessary to limit a range of an effective time for the reading, so the process becomes more complicated. Accordingly, the execution time takes a long time; further, the capacities of the command memory and input memory must be enlarged to write these time information values therein. In some timing, it is probable that the reference to the input memory and the writing to the input memory are carried out in the same clock cycle. Thus, a more complicated process must be required for the pulse input device to read correct input signal information.
Next, problems on construction and operation of the input memory in the conventional pulse input device will be described.
The input circuit 707 samples the input signals 704 at predetermined periods, and detects change thereof, thereafter outputs them as input information to the input memory 708. The sampling is carried out based on a sample clock made by dividing a clock having a predetermined period. The period of the sample clock coincides with the period in which the timer counter is renewed.
In the command memory 705, a plurality of commands for designating input channel numbers and polarities in the signal change (rising edge or falling edge) are contained. Moreover, time information of the signal change as input information obtained by executing the commands is written in predetermined positions respectively. The CPU 703 receives an interrupt signal from the pulse input device, and watches a content of commands stored in the command memory 705 periodically to know a plurality of event times. Moreover, the CPU 703 makes the command memory 705 store a plurality of commands, so as to correctly input the input information even when a plurality of events are generated together in a short time. Incidentally, the CPU 703 and the pulse input device 701 can be operated independently.
The, the sequencer 709 reads the plurality of commands written in the command memory 705 successively, and repeats the series of processes (command scanning). In the command execution, the contents of the input memory 708 corresponding to a channel designated by the command is referred to, and change of the contents is examined, then an operation required is carried out. Thereafter, the operation result is outputted to the command memory 705. Accordingly, the sequencer 709 can detect changes of input signals generated in a time length (hereinafter, this time is called "Command Execution Interval") from execution in command scanning of this time to execution in command scanning of next time by referring to the input memory.
The input memory 708 stores information on the change of input signals sampled in a time corresponding to the command execution interval. Respective commands are executed at constant intervals in a series of command scanning. Accordingly, the information on input signals sampled in the command execution interval is stored in the input memory 708.
The input memory 708 requires 2 bits to store the change information for one sampling in input signals of one channel. Namely, the following three cases:
(1) change from 0 to 1, PA1 (2) change from 1 to 0, and PA1 (3) no change(from 0 to 0 or from 1 to 1)
are considered as the change information obtained by one sampling. Therefore, the number of storage elements required for the input memory is markedly increased. Moreover, the input memory 708 is accessed by both the sequencer 709 and input circuit 707. When the input circuit 707 outputs input information anew, contents or input information stored in the input memory 708 are renewed. The renewal time is not in synchronism with the reading time on which the sequencer 709 executes commands and refers to the input memory. Therefore, the sequencer occasionally cannot obtain correct input information by some timing of the reference. Particularly, this problem is caused when the input memory is renewed and referred to many times while the same command or a plurality of commands are processed in combination as in the phase difference measurement or pulse width measurement.
To solve the problem, there is a conventional device of this sort which includes two input memories, for example, 801 and 802 as shown in FIG. 7. According to the construction, it is possible that the input circuit 707 outputs input information to the input memory 802 while the sequencer 709 refers to the input memory 801 as shown by solid lines in FIG. 7. Thereafter the input circuit 707 outputs input information to the input memory 801 while the sequencer 709 refers to the input memory 802 as shown by broken lines in FIG. 7. In this case, a switching time of the memories is equal to a start time of command scanning in the sequencer 709. Thereby, it can be possible to refer to the same input memory while the same command is scanned. Accordingly, the input information is not mistakenly inputted by the execution order of commands and the execution timing of the sequencer 709, so that a correct result can be obtained even when the same memory is referred to many times.
However, the input memory having the so-called double buffer structure as mentioned above has problems as follows. First, it takes a relatively long time to detect the change of input signals. Namely, the detection delay is markedly large. For example, each input signal is sampled in eight clocks, each command is executed in four clocks, and eight commands are written in the command memory 705. In this case, a time required for one command scanning, i.e., an execution time for all the commands, is 32 clocks.
During the time, the input signals 704 are sampled four times. Namely, it is necessary that the two input memories 801 and 802 accumulate the change information of input signals for four samples respectively. Thus, the number of storage elements required is 16 bits per channel.
At a time 0 (the time gains 1 a clock), the sequencer 609 starts to scan the command memory 705 so as to execute the first command. At the time, the sequencer 709 refers to the input memory 801, and the input circuit 707 outputs data to the input memory 802. At a time of 31, the sequencer 709 completes execution of the eight commands. At a time 32, the input memory 802 is switched to be referred to, next command scanning is started. At the same time 32, the input circuit 707 outputs data to the input memory 801. Next, the detection delay on signal change generated at the time 1 is obtained. Since the input circuit 707 samples the input signals every eight clocks, the signal change generated at the time 1 is contained in the input memory 802 at a time 8. Then, until the time 31, since the sequencer 709 refers to the input memory 801, the signal change in the input memory 802 is not referred to by the sequencer 708. Thereafter, the signal change is referred to by the sequencer 709 at the time 32, but detection delay is generated by execution order of scanning a command for detecting the change. The worst case is that the command is to be executed last in the command scanning. In this case, the command is executed at a time 60. Accordingly, the detection delay from when the signal change is generated to when the change is detected reaches 59 clocks.
As stated above, in the double buffer method, the detection delay becomes at the maximum a value about twice of 32 clocks for which the sequencer 709 refers to the input memory. Moreover, a large scale capacity is required for the input memory. Namely, at the time 0, input information is contained in the input memory 801. However, all the data in the input memory 802 except data contained therein at the time 0 are useless because they are thrown away between the time 8 to 24. Since, the input memory contains such useless data, the capacity must be increased. Since the command execution interval for one command by the sequencer 709 is 32 clocks, ideally, the capacity of the input memory stores data for four times. However, as explained above, an approximately twice input memory capacity is required in the double buffer method.
With with respect to the sequencer in the conventional pulse input device, since the command execution time is changed by rewriting commands in the command memory, overlooked reading or overlapped reading of input signals results. Therefore, it is difficult to obtain correct input information.
With respect to the input memory in the conventional pulse input device, since the memory stores change information of input signals, the storage capacity must be increased. Moreover, in some case, it is impossible to obtain correct input signal information when the input memory is referred to many times during execution of the same command. Though the pulse input device of double buffer method provided with two input memories is used to solve the problem, the detection delay caused on detecting the input signal change by the sequencer is so large. Moreover, the capacity required for the input memory must be increased.